1. Field of the Invention
The present invention relates to memory devices, and particularly to a memory device having reduced test time of memory cells in a test mode.
2. Description of the Background Art
A memory device, such as a dynamic random access memory (DRAM), is generally provided with a circuit for testing a function of each of memory cells constituting a memory cell array.
FIG. 6 is a block diagram showing one example of a conventional memory device. In FIG. 6, a memory cell array 11 comprises a multiplicity of memory cells (not shown) two-dimensionally arranged in row and column directions. Data reading circuits 1 to 4 constituting data reading means respond to a read control signal .phi..sub.R, to be described later, which is supplied from a waveform shaping circuit 9 to read simultaneously data from respective selected memory cells among the memory cells constituting memory cell array 11, amplify the read data, and then apply the amplified data to a data processing circuit 5 as data D.sub.1 to D.sub.4.
When a mode designating signal .phi..sub.T supplied from a signal source, not shown, designates a normal operation mode, data processing circuit 5 serves as a data selecting circuit, selecting any one of the data D.sub.1 to D.sub.4 in response to an address signal .phi..sub.A of four bits supplied from an address signal source, not shown, to provide the selected data as read data D.sub.R . When the mode designating signal .phi..sub.T designates a test mode, data processing circuit 5 serves as an exclusive OR (EX-OR) circuit, providing the signal D.sub.R which indicates whether all of the four data D.sub.1 to D.sub.4 are the same, or at least any one of them is different from the others. Data processing circuit 5 will be described later in detail.
The data D.sub.R provided from data processing circuit 5 is applied to a data output circuit 6. Data output circuit 6 provides the aforementioned data D.sub.R as output data D.sub.O at the timing defined by an output control signal .phi..sub.C supplied from an output control circuit 7 to supply the data D0 to the outside through an external output terminal 8. Data output circuit 6 and output control circuit 7 will be described later in detail.
A row address strobe (RAS) signal supplied from a signal source, not shown, is applied to a timing generating circuit 10, which generates a predetermined timing signal .phi..sub.R ' synchronized with the RAS signal to apply the same to waveform shaping circuit 9.
Waveform shaping circuit 9 comprising two stages of inverters (not shown) applies waveform shaping to the above mentioned timing signal .phi..sub.R ' to generate the read control signal .phi..sub.R and apply the same to output control circuit 7, as well as to data reading circuits 1 to 4 as described above. Output control circuit 7 generates the above mentioned output control signal .phi..sub.C based on the read control signal .phi..sub.R.
FIGS. 7, 8 and 9 are schematic diagrams showing examples of the structures of data processing circuit 5, data output circuit 6 and output control circuit 7, respectively, and FIGS. 10 and 11 are waveform diagrams showing the operation of the conventional memory device shown in FIG. 6. Referring to FIGS. 6 to 11, the operation of the conventional memory device will be hereinafter described in detail.
In the normal operation mode, the mode designating signal .phi..sub.T is assumed to be at a low (L) level. Therefore, in FIG. 7, a switching transistor 57 of a switching circuit 82 in data processing circuit 5 is turned off in response to the signal .phi..sub.T, while a switching transistor 58 of switching circuit 82 is turned on in response to an inverted signal of the signal .phi..sub.T by an inverter 59.
Also, in the normal operation mode, four bits (.phi..sub.A1, .phi..sub.A2, .phi..sub.A3, .phi..sub.A4) of the address signal .phi..sub.A are applied to the control inputs of switching transistors 51 to 54 of a selecting circuit 81, respectively, so that only one of them is turned on. Accordingly, only one data, among the four input data D.sub.1 to D.sub.4, corresponding to the switching transistor which is turned on is provided as read data D.sub.R through the corresponding transistor and transistor 58 of switching circuit 82.
In the test mode, on the other hand, the mode designating signal .phi..sub.T is assumed to be at a high (H) level. Therefore, in FIG. 7, switching transistor 57 of switching circuit 82 in data processing circuit 5 is turned on in response to the signal .phi..sub.T, while switching transistor 58 of switching circuit 82 is turned off in response to an inverted signal of the signal .phi..sub.T by inverter 59.
In the test mode, the address signal .phi..sub.A for selecting read data is invalid, and the above described data selection is not carried out. Instead, the four data D.sub.1 to D.sub.4 are exclusive-ORed by an EX-OR gate 55 in a logic operation circuit 83, and the result is provided as the read data D.sub.R through an inverter 56 and transistor 57. As a result, when all of the four data D.sub.1 to D.sub.4 read from the memory cell array coincide with each other, the read data D.sub.R at an H level is provided, and in the other cases the read data D.sub.R at an L level is provided.
The output control signal .phi..sub.C supplied from output control circuit 7 comprising two stage of inverters 71 and 72, as shown in FIG. 9, is a control signal which is inactive at an L level, and is assumed to be in the inactive state during a period corresponding to read data of a so-called invalid address (invalid data) in memory cell array 11, based on the read control signal .phi..sub.R synchronized with the RAS signal.
Referring to FIG. 10 in which the operation in the normal operation mode is shown, the read data D.sub.R (FIG. 10(b)) is invalid data corresponding to an invalid address during the period the output control signal .phi..sub.C (FIG. 10 (a)) is at an L level, so that the output D.sub.O (FIG. 10 (c)) of data output circuit 6 comprising an NAND gate 61 and an inverter 62, as shown in FIG. 8, is rendered in a high impedance state (Hi-Z).
With the address of read data changing from invalid to valid, the read data D.sub.R changes from invalid data to valid data (FIG. 10 (b)). The control signal .phi..sub.C (FIG. 10 (a)) rises to an H level at a timing defined in advance with respect to the timing of this change to be in the active state. As a result, data output circuit 6 of FIG. 8 provides the data D.sub.R supplied from data processing circuit 5 to the outside as the output data D.sub.O (FIG. 10 (c)).
Referring to FIG. 11 in which the operation in the test mode is shown, the basic operation is the same as that shown in FIG. 10, except that the read data D.sub.R (FIG. 11(b)) is not the one selected from the four data D.sub.1 to D.sub.4, but the one obtained by EX-OR processing of the data D.sub.1 to D.sub.4. However, it should be noticed that time required for the EX-OR operation causes delay by a certain time period in the timing of change of the read data D.sub.R from invalid to valid in the test mode, with respect to the timing of such change of the read data D.sub.R in the nominal operation mode.
Also in the test mode, the output control signal .phi..sub.C has the same waveform as in the normal operation mode, as shown by the solid line (FIG. 11 (a)), which results in partial output of the invalid data D.sub.R as the output data D.sub.O from data output circuit 6, as shown by the solid line of FIG. 11 (c).
The following problem arises in the conventional memory device having the structure described above. In the test mode, when the read data D.sub.R changes from invalid to valid at the timing shogun in FIG. 11 (b) (the timing later than that in the normal operation mode of FIG. 10 (b)), a part of the invalid data is once provided as the data output D.sub.O as shown by the solid line of FIG. 11 (c) because the waveform of the output control signal .phi..sub.C is fixed. Time required for change of the once-provided invalid data to valid data causes significant delay in output of the original valid data. Therefore, in the conventional memory device described above, the problem arises that access time of valid data in the test mode becomes long, resulting in a long time required for a function test of the memory device.
Accordingly, if the timing when the output control signal .phi..sub.C rises is delayed as shown by the broken line of FIG. 11 (a), the output data D.sub.0 in the high impedance state changes to valid data at the timing shown by the broken line of FIG. 11 (c), so that the output of invalid data as described above can be prevented, and consequently delay in the timing of reading in the test mode can be reduced.
The delay in rise of the output control signal .phi..sub.C, however, causes delay in rise of the signal .phi..sub.C also in the normal operation mode, so that the problem arises that high speed operation of the memory device in the normal operation mode is difficult to be performed.